555 search results - page 28 / 111 » Iris Recognition Algorithm Optimized for Hardware Implementa... |
136
Voted
EUROPAR
2008
Springer
15 years 5 months ago
2008
Springer
Abstract. Understanding program behavior is at the foundation of program optimization. Techniques for automatic recognition of program constructs characterize the behavior of code ...
110
Voted
DSD
2008
IEEE
15 years 10 months ago
2008
IEEE
Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication inte...
121
Voted
ASAP
2006
IEEE
15 years 9 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
135
Voted
ICMCS
2009
IEEE
15 years 1 months ago
2009
IEEE
Parallel scalability allows an application to efficiently utilize an increasing number of processing elements. In this paper we explore a design space for parallel scalability for...
127
Voted
ICCAD
2001
IEEE
16 years 17 days ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...