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CASES
2006
ACM
14 years 1 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
BROADNETS
2005
IEEE
14 years 1 months ago
Multi-rate throughput optimization for wireless local area network anomaly problem
— Due to varying wireless channel conditions, the IEEE 802.11 wireless local area network (WLAN) standard supports multiple modulation types to accommodate the tradeoff between d...
Yu-Liang Kuo, Kun-Wei Lai, Frank Yeong-Sung Lin, Y...
IEEEPACT
2005
IEEE
14 years 1 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
SERA
2004
Springer
14 years 28 days ago
NuEditor - A Tool Suite for Specification and Verification of NuSCR
NuEditor is a tool suite supporting specification and verification of software requirements written in NuSCR. NuSCR extends SCR (Software Cost Reduction) notation that has been us...
Jaemyung Cho, Junbeom Yoo, Sung Deok Cha
GECCO
2003
Springer
415views Optimization» more  GECCO 2003»
14 years 24 days ago
Evolutionary Algorithms for Two Problems from the Calculus of Variations
Abstract. A brachistochrone is the path along which a weighted particle falls most quickly from one point to another, and a catenary is the smooth curve connecting two points whose...
Bryant A. Julstrom