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CC
2007
Springer
107views System Software» more  CC 2007»
14 years 1 months ago
A Fast Cutting-Plane Algorithm for Optimal Coalescing
Abstract. Recent work has shown that the subtasks of register allocation (spilling, register assignment, and coalescing) can be completely separated. This work presents an algorith...
Daniel Grund, Sebastian Hack
EUROPAR
2001
Springer
13 years 12 months ago
Using a Swap Instruction to Coalesce Loads and Stores
A swap instruction, which exchanges a value in memory with a value of a register, is available on many architectures. The primary application of a swap instruction has been for pro...
Apan Qasem, David B. Whalley, Xin Yuan, Robert van...
IEEEPACT
2002
IEEE
14 years 12 days ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
CC
2010
Springer
117views System Software» more  CC 2010»
14 years 2 months ago
Punctual Coalescing
Compilers use register coalescing to avoid generating code for copy instructions. For architectures with register aliasing such as x86, Smith, Ramsey, and Holloway (2004) presented...
Fernando Magno Quintão Pereira, Jens Palsbe...
CGO
2004
IEEE
13 years 11 months ago
Optimizing Translation Out of SSA Using Renaming Constraints
Static Single Assignment form is an intermediate representation that uses instructions to merge values at each confluent point of the control flow graph. instructions are not ma...
Fabrice Rastello, François de Ferriè...