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ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
CSCW
2010
ACM
14 years 6 months ago
2010
ACM
People are often required to catch up on information they have missed in meetings, because of lateness or scheduling conflicts. Catching up is a complex cognitive process where pe...
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
LCTRTS
2010
Springer
14 years 4 months ago
2010
Springer
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...