Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
Irregular and iterative I/O-intensive jobs need a different approach from parallel job schedulers. The focus in this case is not only the processing requirements anymore: memory, ...
Abstract We state some of the most important open algorithmic problems in real-time scheduling, and survey progress made on these problems since the 2009 Dagstuhl scheduling semina...
The elastic task model proposed by Buttazzo, et. al. [9] is a powerful model for adapting real-time systems in the presence of uncertainty. This paper generalizes the existing ela...
Thidapat Chantem, Xiaobo Sharon Hu, Michael D. Lem...