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» Kestrel: Design of an 8-bit SIMD Parallel Processor
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IPPS
2002
IEEE
14 years 12 days ago
Implementing Associative Search and Responder Resolution
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
Meiduo Wu, Robert A. Walker, Jerry L. Potter
ICPPW
2006
IEEE
14 years 1 months ago
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
Sam Sander, Linda M. Wills
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
14 years 1 months ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speciï¬...
Robert L. Bocchino Jr., Vikram S. Adve
ITCC
2005
IEEE
14 years 1 months ago
On the Masking Countermeasure and Higher-Order Power Analysis Attacks
Abstract— Masking is a general method used to thwart Differential Power Analysis, in which all the intermediate data inside an implementation are XORed with random Boolean values...
François-Xavier Standaert, Eric Peeters, Je...
VLDB
2007
ACM
121views Database» more  VLDB 2007»
14 years 1 months ago
CellSort: High Performance Sorting on the Cell Processor
In this paper we describe the design and implementation of CellSort − a high performance distributed sort algorithm for the Cell processor. We design CellSort as a distributed b...
Bugra Gedik, Rajesh Bordawekar, Philip S. Yu