11 search results - page 1 / 3 » L0 buffer energy optimization through scheduling and explora... |
SAC
2004
ACM
14 years 4 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
LCTRTS
2007
Springer
14 years 5 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
TCSV
2008
13 years 11 months ago
2008
The objective of dynamic voltage scaling (DVS) is to adapt the frequency and voltage for configurable platforms to obtain energy savings. DVS is especially attractive for video dec...
ECRTS
2004
IEEE
14 years 2 months ago
2004
IEEE
In this paper, we explore the feasibility and performance optimization problems for real-time systems that must remain functional during an operation/mission with a fixed, initial...
JSA
2007
13 years 11 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...