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» Large-scale capacitance calculation
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ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
DATE
2005
IEEE
147views Hardware» more  DATE 2005»
14 years 2 months ago
Buffer Insertion Considering Process Variation
A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point o...
Jinjun Xiong, King Ho Tam, Lei He
PATMOS
2005
Springer
14 years 1 months ago
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
CGF
2008
151views more  CGF 2008»
13 years 8 months ago
Reconstructing head models from photographs for individualized 3D-audio processing
Visual fidelity and interactivity are the main goals in Computer Graphics research, but recently also audio is assuming an important role. Binaural rendering can provide extremely...
Matteo Dellepiane, Nico Pietroni, Tsingos Tsingos,...
BMCBI
2005
94views more  BMCBI 2005»
13 years 8 months ago
Measuring similarities between transcription factor binding sites
Background: Collections of transcription factor binding profiles (Transfac, Jaspar) are essential to identify regulatory elements in DNA sequences. Subsets of highly similar profi...
Szymon M. Kielbasa, Didier Gonze, Hanspeter Herzel