601 search results - page 108 / 121 » Lattice-based memory allocation |
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
The combination of increasing component power consumption, a desire for denser systems, and the required performance growth in the face of technology-scaling issues are posing eno...
PADS
2003
ACM
14 years 26 days ago
2003
ACM
Wireless networks’ models differ from wired ones at least in the innovative dynamic effects of host-mobility and open-broadcast nature of the wireless medium. Topology changes d...
GECCO
2009
Springer
13 years 5 months ago
2009
Springer
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...