1658 search results - page 3 / 332 » Layout of Bayesian Networks |
APCCAS
2002
IEEE
14 years 13 days ago
2002
IEEE
The pyramid networks are well-known as suitable structures for parallel computations such as image processing. This paper shows a practical 3D VLSI layout of the N-vertex pyramid ...
ICN
2001
Springer
13 years 12 months ago
2001
Springer
SOFSEM
1997
Springer
13 years 11 months ago
1997
Springer
This paper surveys recent results in the area of virtual path layout in ATM networks. We present a model for the theoretical study of these layouts the model amounts to covering t...
ICPP
2000
IEEE
13 years 12 months ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
GD
2009
Springer
13 years 10 months ago
2009
Springer
We describe an algorithm for radial layout of undirected graphs, in which nodes are constrained to concentric circles centered at the origin. Such constraints are typical, e.g., i...