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» Layout synthesis for datapath designs
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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 1 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
14 years 8 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
ITCC
2005
IEEE
15 years 10 months ago
Performance Analysis of Mobile Backbone Topology Synthesis Algorithm for Wireless Ad Hoc Networks
In this paper, we present a scalable fully distributed version of a Mobile Backbone Network Topology Synthesis Algorithm (MBN-TSA) for constructing and maintaining a dynamic backb...
Laura Huei-jiun Ju, Izhak Rubin
TVLSI
2002
366views more  TVLSI 2002»
15 years 3 months ago
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 8 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith