Sciweavers

129 search results - page 22 / 26
» Layout synthesis for datapath designs
Sort
View
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 5 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
13 years 9 days ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
ITCC
2005
IEEE
14 years 2 months ago
Performance Analysis of Mobile Backbone Topology Synthesis Algorithm for Wireless Ad Hoc Networks
In this paper, we present a scalable fully distributed version of a Mobile Backbone Network Topology Synthesis Algorithm (MBN-TSA) for constructing and maintaining a dynamic backb...
Laura Huei-jiun Ju, Izhak Rubin
TVLSI
2002
366views more  TVLSI 2002»
13 years 8 months ago
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
14 years 20 days ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith