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CIB
2005
125views more  CIB 2005»
13 years 8 months ago
An On-Line Web Visualization System with Filtering and Clustering Graph
A Web graph refers to the graph that is used to represent relationships between Web pages in cyberspace, where a node represents a URL and an edge indicates a link between two URLs...
Wei Lai, Xiaodi Huang, Ronald Wibowo, Jiro Tanaka
DAC
2005
ACM
13 years 10 months ago
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J...
ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
14 years 29 days ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
CAIP
2009
Springer
140views Image Analysis» more  CAIP 2009»
14 years 4 days ago
Hierarchical Decomposition of Handwritten Manuscripts Layouts
Abstract. In this paper we propose a new approach to improve electronic editions of literary corpus, providing an efficient estimation of manuscripts pages structure. In any handwr...
Vincent Malleron, Véronique Eglin, Hubert E...
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Placement with symmetry constraints for analog layout design using TCG-S
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module...
Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hu...