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» Leakage power modeling and reduction with data retention
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MTDT
2006
IEEE
154views Hardware» more  MTDT 2006»
14 years 2 months ago
SRAM Cell Current in Low Leakage Design
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, C...
ICPP
2009
IEEE
13 years 6 months ago
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
Matteo Monchiero, Ramon Canal, Antonio Gonzá...
PATMOS
2010
Springer
13 years 6 months ago
L1 Data Cache Power Reduction Using a Forwarding Predictor
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
P. Carazo, R. Apolloni, Fernando Castro, Daniel Ch...
PATMOS
2007
Springer
14 years 2 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
CORR
2011
Springer
206views Education» more  CORR 2011»
13 years 5 days ago
A Study of Language Usage Evolution in Open Source Software
: In December of 2010, the new game CityVille achieved 6 million daily active users in just 8 days. Clearly the success of CityVille owes something to the fun gameplay experience i...
Siim Karus, Harald Gall