28 search results - page 4 / 6 » Learning heuristics for basic block instruction scheduling |
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
EMSOFT
2010
Springer
13 years 5 months ago
2010
Springer
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
DAGSTUHL
2001
13 years 9 months ago
2001
Visualization of an algorithm offers only a rough picture of operations. Explanations are crucial for deeper understanding, because they help the viewer to associate the visualiza...