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ERSA
2010
186views Hardware» more  ERSA 2010»
13 years 8 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
TEI
2009
ACM
117views Hardware» more  TEI 2009»
14 years 4 months ago
Easigami: a reconfigurable folded-sheet TUI
Easigami is a novel tangible user interface (TUI) and interactive system intended to help children to learn to fold 3D geometric forms and to explore 2D-3D transformations. We pre...
Yingdan Huang, Mark D. Gross, Ellen Yi-Luen Do, Mi...
FPGA
2006
ACM
117views FPGA» more  FPGA 2006»
14 years 1 months ago
Context-free-grammar based token tagger in reconfigurable devices
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
Young H. Cho, James Moscola, John W. Lockwood
FPL
2006
Springer
96views Hardware» more  FPL 2006»
14 years 1 months ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 11 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu