331 search results - page 13 / 67 » Limits on Multiple Instruction Issue |
EUROMICRO
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
IOR
2010
13 years 6 months ago
2010
We study a stochastic network that consists of two servers shared by two classes of jobs. Class 1 jobs require a concurrent occupancy of both servers while class 2 jobs use one se...
CGO
2005
IEEE
14 years 2 months ago
2005
IEEE
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
ICMCS
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we propose a hybrid architecture to integrate Peer-to-Peer (P2P) streaming approaches with content distribution networks (CDNs). We further utilize Multiple Descrip...
IPPS
1996
IEEE
14 years 29 days ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...