331 search results - page 23 / 67 » Limits on Multiple Instruction Issue |
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
ISCA
2002
IEEE
13 years 8 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...