Sciweavers

331 search results - page 24 / 67
» Limits on Multiple Instruction Issue
Sort
View
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
14 years 5 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...
IUI
2006
ACM
14 years 2 months ago
Are two talking heads better than one?: when should use more than one agent in e-learning?
Recent interest in the use of software character agents raises the issue of how many agents should be used in online learning. In this paper we review evidence concerning the rela...
Hua Wang, Mark H. Chignell, Mitsuru Ishizuka
ASAP
2004
IEEE
127views Hardware» more  ASAP 2004»
14 years 16 days ago
A Public-Key Cryptographic Processor for RSA and ECC
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vi...
IEEEPACT
2006
IEEE
14 years 2 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
CODES
2009
IEEE
14 years 21 days ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...