331 search results - page 34 / 67 » Limits on Multiple Instruction Issue |
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
IEEEPACT
1998
IEEE
14 years 1 months ago
1998
IEEE
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...
VLDB
1999
ACM
14 years 1 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
CASES
2008
ACM
13 years 10 months ago
2008
ACM
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...