331 search results - page 3 / 67 » Limits on Multiple Instruction Issue |
ISCA
1997
IEEE
14 years 24 days ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
HPCA
1995
IEEE
14 years 4 days ago
1995
IEEE
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
ISCA
1996
IEEE
14 years 22 days ago
1996
IEEE
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads th...
LCTRTS
1998
Springer
14 years 24 days ago
1998
Springer
Instruction scheduling is a necessary step in compiling for many modern microprocessors. Traditionally, global instruction scheduling techniques have outperformed local techniques....