331 search results - page 40 / 67 » Limits on Multiple Instruction Issue |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
EMNLP
2010
13 years 5 months ago
2010
In this paper, we develop multilingual supervised latent Dirichlet allocation (MLSLDA), a probabilistic generative model that allows insights gleaned from one language's data...
JETC
2008
13 years 6 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
TCOM
2008
13 years 7 months ago
2008
Abstract-- Input-queued cell switches employing the oldestcell-first (OCF) policy have been shown to yield low mean delay characteristics. Moreover, it has been proven that OCF is ...
CORR
2002
Springer
13 years 7 months ago
2002
Springer
Computational Grids are emerging as a new infrastructure for Internet-based parallel and distributed computing. They enable the sharing, exchange, discovery, and aggregation of re...