331 search results - page 47 / 67 » Limits on Multiple Instruction Issue |
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
ICSE
2000
IEEE-ACM
13 years 11 months ago
2000
IEEE-ACM
A workshop was held at ICSE 2000 in Limerick, Ireland to further efforts in the development of a standard exchange format (SEF) for data extracted from and about source code. WoSE...
ISPDC
2010
IEEE
13 years 6 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
DSN
2005
IEEE
14 years 1 months ago
2005
IEEE
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...