331 search results - page 5 / 67 » Limits on Multiple Instruction Issue |
ISCA
1995
IEEE
14 years 11 days ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
ICS
2004
Tsinghua U.
14 years 2 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
ICCD
2000
IEEE
14 years 5 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
IEEEPACT
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
HPCA
1999
IEEE
14 years 1 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...