Sciweavers

227 search results - page 19 / 46
» Limits to the Performance of Software Shared Memory: A Layer...
Sort
View
SC
2009
ACM
14 years 2 months ago
Enabling software management for multicore caches with a lightweight hardware support
The management of shared caches in multicore processors is a critical and challenging task. Many hardware and OS-based methods have been proposed. However, they may be hardly adop...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
14 years 1 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
PDP
2005
IEEE
14 years 1 months ago
A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol
SVM systems are a cheaper and flexible way to implement the shared memory programming paradigm. Their huge flexibility is due to their software implementation; however, this is al...
Salvador Petit, Julio Sahuquillo, Ana Pont
SBMF
2009
Springer
184views Formal Methods» more  SBMF 2009»
14 years 2 months ago
Concolic Testing of the Multi-sector Read Operation for Flash Memory File System
In today’s information society, flash memory has become a virtually indispensable component, particularly for mobile devices. In order for mobile devices to operate successfully...
Moonzoo Kim, Yunho Kim
SP
2003
IEEE
116views Security Privacy» more  SP 2003»
14 years 1 months ago
Garbage Collector Memory Accounting in Language-Based Systems
Language run-time systems are often called upon to safely execute mutually distrustful tasks within the same runtime, protecting them from other tasks’ bugs or otherwise hostile...
David W. Price, Algis Rudys, Dan S. Wallach