Sciweavers

291 search results - page 31 / 59
» Linear Types for Packet Processing
Sort
View
FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
14 years 24 days ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
MSWIM
2009
ACM
14 years 2 months ago
How do wireless chains behave?: the impact of MAC interactions
In a Multi-hop Wireless Networks (MHWN), packets are routed between source and destination using a chain of intermediate nodes; chains are a fundamental communication structure in...
Saquib Razak, Vinay Kolar, Nael B. Abu-Ghazaleh, K...
ICIP
2010
IEEE
13 years 5 months ago
Hyperspectral image segmentation and unmixing using hidden Markov trees
This paper is concerned with joint Bayesian endmember extraction and linear unmixing of hyperspectral images using a spatial prior on the abundance vectors. We hypothesize that hy...
Roni Mittelman, Alfred O. Hero III
COMCOM
2007
111views more  COMCOM 2007»
13 years 7 months ago
An argument for simple embedded ACL optimisation
The difficulty of efficiently reordering the rules in an Access Control List is considered and the essential optimisation problem formulated. The complexity of exact and sophistic...
Vic Grout, John Davies, John McGinn
ICON
2007
IEEE
14 years 1 months ago
Definition and Implementation of Logical Function Blocks Compliant to ForCES Specification
—IETF ForCES (Forwarding and Control Element Separation) is defining specifications for interfaces and modular resources abstractions in open programmable network equipments. Acc...
Ligang Dong, Fenggen Jia, Weiming Wang