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ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
14 years 1 months ago
Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video
Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell ...
Rafal Karakiewicz, Roman Genov
SCOPES
2004
Springer
14 years 1 months ago
An Integer Linear Programming Approach to Classify the Communication in Process Networks
New embedded signal processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable uni...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
CSCLP
2007
Springer
14 years 2 months ago
Quasi-Linear-Time Algorithms by Generalisation of Union-Find in CHR
Abstract. The union-find algorithm can be seen as solving simple equations between variables or constants. With a few lines of code change, we generalise its implementation in CHR...
Thom W. Frühwirth
COCOON
2009
Springer
14 years 2 months ago
Limits to List Decoding Random Codes
It has been known since [Zyablov and Pinsker 1982] that a random q-ary code of rate 1 − Hq(ρ) − ε (where 0 < ρ < 1 − 1/q, ε > 0 and Hq(·) is the q-ary entropy ...
Atri Rudra
CCR
2006
115views more  CCR 2006»
13 years 8 months ago
Network coding: an instant primer
Network coding is a new research area that may have interesting applications in practical networking systems. With network coding, intermediate nodes may send out packets that are...
Christina Fragouli, Jean-Yves Le Boudec, Jörg...