Abstract. We summarize and reorganize some of the last decade's research on real-time extensions of temporal logic. Our main focus is on tableau constructions for model checki...
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
The coincidence between the model-theoretic and the procedural semantics of SLDresolution does not carry over to a Prolog system that also implements non-logical features like cut...
We prove that the set of all Lambertian reflectance functions (the mapping from surface normals to intensities) obtained with arbitrary distant light sources lies close to a 9D lin...
The syntenic dista nce between two species is the minimum number of fusions, fissions, and translocations required to transform one genome into the other. The linear syntenic dis...