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118
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CONCUR
1998
Springer
15 years 7 months ago
It's About Time: Real-Time Logics Reviewed
Abstract. We summarize and reorganize some of the last decade's research on real-time extensions of temporal logic. Our main focus is on tableau constructions for model checki...
Thomas A. Henzinger
134
Voted
FPGA
2008
ACM
145views FPGA» more  FPGA 2008»
15 years 5 months ago
FPGA interconnect design using logical effort
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
125
Voted
ENTCS
2000
123views more  ENTCS 2000»
15 years 3 months ago
Defining Standard Prolog in Rewriting Logic
The coincidence between the model-theoretic and the procedural semantics of SLDresolution does not carry over to a Prolog system that also implements non-logical features like cut...
Marija Kulas, Christoph Beierle
ICCV
2001
IEEE
16 years 5 months ago
Lambertian Reflectance and Linear Subspaces
We prove that the set of all Lambertian reflectance functions (the mapping from surface normals to intensities) obtained with arbitrary distant light sources lies close to a 9D lin...
Ronen Basri, David W. Jacobs
134
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CPM
2000
Springer
105views Combinatorics» more  CPM 2000»
15 years 8 months ago
Structural Properties and Tractability Results for Linear Synteny
The syntenic dista nce between two species is the minimum number of fusions, fissions, and translocations required to transform one genome into the other. The linear syntenic dis...
David Liben-Nowell, Jon M. Kleinberg