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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 4 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 4 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
WILF
2007
Springer
170views Fuzzy Logic» more  WILF 2007»
14 years 1 months ago
Time-Series Alignment by Non-negative Multiple Generalized Canonical Correlation Analysis
Background: Quantitative analysis of differential protein expressions requires to align temporal elution measurements from liquid chromatography coupled to mass spectrometry (LC/M...
Bernd Fischer, Volker Roth, Joachim M. Buhmann
CCGRID
2006
IEEE
14 years 1 months ago
Component-Based Modeling, Analysis and Animation
Component-based software construction is widely used in a variety of applications, from embedded environments to grid computing. However, errors in these applications and systems ...
Jeff Kramer