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» Linear-Time Algorithms in Memory Hierarchies
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ASPLOS
2010
ACM
14 years 2 months ago
Flexible architectural support for fine-grain scheduling
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis
DRR
2010
13 years 9 months ago
Time and space optimization of document content classifiers
Scaling up document-image classifiers to handle an unlimited variety of document and image types poses serious challenges to conventional trainable classifier technologies. Highly...
Dawei Yin, Henry S. Baird, Chang An
PVLDB
2008
137views more  PVLDB 2008»
13 years 6 months ago
Flashing up the storage layer
In the near future, commodity hardware is expected to incorporate both flash and magnetic disks. In this paper we study how the storage layer of a database system can benefit from...
Ioannis Koltsidas, Stratis Viglas
TON
2008
124views more  TON 2008»
13 years 7 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown
INFOCOM
1999
IEEE
13 years 11 months ago
High Performance IP Routing Table Lookup using CPU Caching
Wire-speed IP (Internet Protocol) routers require very fast routing table lookup for incoming IP packets. The routing table lookup operation is time consuming because the part of ...
Tzi-cker Chiueh, Prashant Pradhan