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WSC
1997
13 years 11 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
VLDB
2002
ACM
129views Database» more  VLDB 2002»
13 years 9 months ago
Optimizing View Queries in ROLEX to Support Navigable Result Trees
An increasing number of applications use XML data published from relational databases. For speed and convenience, such applications routinely cache this XML data locally and acces...
Philip Bohannon, Sumit Ganguly, Henry F. Korth, P....
RTSS
2005
IEEE
14 years 3 months ago
Preemptible Atomic Regions for Real-Time Java
nt a new concurrency control abstraction for real-time systems called preemptible atomic regions (PARs). PARs a transactional mechanism that improves upon lock-based mutual exclus...
Jeremy Manson, Jason Baker, Antonio Cunei, Suresh ...
ICMCS
2006
IEEE
144views Multimedia» more  ICMCS 2006»
14 years 3 months ago
Generating a Time Shrunk Lecture Video by Event Detection
Streaming a lecture video via the Internet is important for Elearning. We have developed a system that generates a lecture video using virtual camerawork based on shooting techniq...
Takao Yokoi, Hironobu Fujiyoshi
HPCA
2011
IEEE
13 years 1 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...