1929 search results - page 105 / 386 » Load Balancing with Memory |
112
Voted
JILP
2000
15 years 2 months ago
2000
We identify that a set of multimedia applications exhibit highly regular read-after-read (RAR) and read-after-write (RAW) memory dependence streams. We exploit this regularity to ...
108
Voted
ICS
2009
Tsinghua U.
15 years 9 months ago
2009
Tsinghua U.
General purpose programming on the graphics processing units (GPGPU) has received a lot of attention in the parallel computing community as it promises to offer the highest perfo...
109
Voted
IEEEPACT
2006
IEEE
15 years 8 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
144
Voted
HPCA
2000
IEEE
15 years 7 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
102
Voted
ISCA
1998
IEEE
15 years 6 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...