1929 search results - page 371 / 386 » Load Balancing with Memory |
ECRTS
2006
IEEE
14 years 3 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
INFOCOM
2006
IEEE
14 years 3 months ago
2006
IEEE
— In this paper, we propose a simulation framework, TranSim, that reduces the rate at which packet-events are generated, in order to accelerate large-scale simulation of IP netwo...
VLDB
2004
ACM
14 years 2 months ago
2004
ACM
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
ISCA
2003
IEEE
14 years 2 months ago
2003
IEEE
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
RTSS
2003
IEEE
14 years 2 months ago
2003
IEEE
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...