141 search results - page 24 / 29 » Load Execution Latency Reduction |
110
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ICPP
1999
IEEE
15 years 6 months ago
1999
IEEE
This paper describes a technique called producer-push that enhances the performance of a page-based software distributed shared memory system. Shared data, in software DSM systems...
116
Voted
MICRO
1997
IEEE
15 years 6 months ago
1997
IEEE
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
161
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ISCA
1995
IEEE
15 years 6 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
147
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ISCA
1995
IEEE
15 years 6 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
116
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EUROPAR
2009
Springer
15 years 9 months ago
2009
Springer
With the increasing use of large image and video archives and high-resolution multimedia data streams in many of today’s research and application areas, there is a growing need f...