Sciweavers

1631 search results - page 277 / 327
» Load balancing on speed
Sort
View
HPCA
2005
IEEE
15 years 9 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
SC
2005
ACM
15 years 9 months ago
The Globus Striped GridFTP Framework and Server
The GridFTP extensions to the File Transfer Protocol define a general-purpose mechanism for secure, reliable, high-performance data movement. We report here on the Globus striped ...
William E. Allcock, John Bresnahan, Rajkumar Ketti...
WMPI
2004
ACM
15 years 9 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
15 years 9 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
PERCOM
2003
ACM
15 years 9 months ago
Study of Distance Vector Routing Protocols for Mobile Ad Hoc Networks
We investigate the performance issues of destinationsequenced distance vector (DSDV) and ad-hoc on-demand distance vector (AODV) routing protocols for mobile ad hoc networks. Four...
Yi Lu, Weichao Wang, Yuhui Zhong, Bharat K. Bharga...