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DFT
2006
IEEE
130views VLSI» more  DFT 2006»
14 years 1 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
ECRTS
2006
IEEE
14 years 1 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
NPAR
2006
ACM
14 years 1 months ago
Real-time pencil rendering
ROJECTPROJECT ABSTRACTABSTRACTABSTRACT After achieving real-time photorealistic rendering, the computer graphics community is beginning to turn its attention to non-photorealistic ...
Hyunjun Lee, Sungtae Kwon, Seungyong Lee
INFOCOM
2005
IEEE
14 years 1 months ago
Design and implementation of network puzzles
Abstract— Client puzzles have been proposed in a number of protocols as a mechanism for mitigating the effects of distributed denial of service (DDoS) attacks. In order to provid...
Wu-chi Feng, Edward C. Kaiser, A. Luu