Delay modeling and static timing analysis for MTCMOS circuits

- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy. Key words: MTCMOS, Selective-MT, Delay, Static timing analysis, Leakage power, Interpolation. I. Background As the transistor technology gets advanced, low-power design techniques become significantly important. In particular, leakage power reduction is strongly required in the LSI for portable information devices to prolong the battery life. In addition, high performance is also needed in the ...

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Naoaki Ohkubo, Kimiyoshi Usami
• Keywords: ASPDAC 2006, Circuit Delay, Leakage Power, Static Timing Analysis