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TC
2011
13 years 2 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
TC
2008
13 years 7 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
CONEXT
2008
ACM
13 years 9 months ago
Distributed content delivery using load-aware network coordinates
To scale to millions of Internet users with good performance, content delivery networks (CDNs) must balance requests between content servers while assigning clients to nearby serv...
Nicholas Ball, Peter R. Pietzuch
LCPC
2009
Springer
14 years 6 days ago
A Balanced Approach to Application Performance Tuning
Abstract. Current hardware trends place increasing pressure on programmers and tools to optimize scientific code. Numerous tools and techniques exist, but no single tool is a pana...
Souad Koliai, Stéphane Zuckerman, Emmanuel ...
EUROMICRO
2007
IEEE
14 years 2 months ago
A Performance Evaluation of RSerPool Server Selection Policies in Varying Heterogeneous Capacity Scenarios
Reliable Server Pooling (RSerPool) is a protocol framework for server redundancy and session failover, currently still under standardization by the IETF RSerPool WG. Server redund...
Thomas Dreibholz, Xing Zhou, Erwin P. Rathgeb