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MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
14 years 2 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 2 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
SI3D
2005
ACM
14 years 2 months ago
Texture sprites: texture elements splatted on surfaces
We present a new interactive method to texture complex geometries at very high resolution, while using little memory and without the need for a global planar parameterization. We ...
Sylvain Lefebvre, Samuel Hornus, Fabrice Neyret
CONCUR
2005
Springer
14 years 2 months ago
Concurrent Clustered Programming
d Abstract) Vijay Saraswat1 and Radha Jagadeesan2 1 IBM T.J. Watson Research Lab 2 School of CTI, DePaul University Abstract. We present the concurrency and distribution primitives...
Vijay A. Saraswat, Radha Jagadeesan
SG
2005
Springer
14 years 1 months ago
Multi-level Interaction in Parametric Design
Parametric design systems model a design as a constrained collection of schemata. Designers work in such systems at two levels: definition of schemata and constraints; and search w...
Robert Aish, Robert Woodbury
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