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» Locating cache performance bottlenecks using data profiling
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118
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IEEEPACT
2006
IEEE
15 years 8 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
IEEEPACT
2009
IEEE
15 years 8 days ago
Region Based Structure Layout Optimization by Selective Data Copying
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
Sandya S. Mannarswamy, Ramaswamy Govindarajan, Ris...
145
Voted
USENIX
1994
15 years 3 months ago
Reducing File System Latency using a Predictive Approach
Despite impressive advances in file system throughput resulting from technologies such as high-bandwidth networks and disk arrays, file system latency has not improved and in many...
Jim Griffioen, Randy Appleton
108
Voted
CGF
2008
125views more  CGF 2008»
15 years 2 months ago
Interactive Visualization for Memory Reference Traces
We present the Memory Trace Visualizer (MTV), a tool that provides interactive visualization and analysis of the sequence of memory operations performed by a program as it runs. A...
A. N. M. Imroz Choudhury, Kristin C. Potter, Steve...
131
Voted
ICS
2003
Tsinghua U.
15 years 7 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman