1749 search results - page 224 / 350 » Logic, Optimization, and Constraint Programming |
128
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CODES
2007
IEEE
15 years 9 months ago
2007
IEEE
There is a strong need now for compilers of embedded systems to find effective ways of optimizing series of loop-nests, wherein majority of the memory references occur in the fo...
119
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ASPDAC
2008
ACM
15 years 5 months ago
2008
ACM
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
115
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ICRA
2002
IEEE
15 years 8 months ago
2002
IEEE
— Closed-loop, asymptotically stable walking motions are designed for a 5-link, planar bipedal robot model with one degree of underactuation. Parameter optimization is applied to...
135
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IEEEPACT
1998
IEEE
15 years 7 months ago
1998
IEEE
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...
152
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IJRR
2007
15 years 3 months ago
2007
An algorithm is presented for wheeled mobile robot trajectory generation that achieves a high degree of generality and efficiency. The generality derives from numerical lineariza...