In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
In this paper, we describe a receding horizon scheme that satisfies a class of linear temporal logic specifications sufficient to describe a wide range of properties including saf...
Tichakorn Wongpiromsarn, Ufuk Topcu, Richard M. Mu...
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
We consider a formal framework for property verification of web applications using Spin model checker. Some of the web related properties concern all states of the model, while ot...
May Haydar, Sergiy Boroday, Alexandre Petrenko, Ho...
Mixed-Integer Programs (MIP's) involving logical implications modelled through big-M coefficients, are notoriously among the hardest to solve. In this paper we propose and an...