233 search results - page 10 / 47 » Logic design for low-voltage low-power CMOS circuits |
CORR
2008
Springer
13 years 8 months ago
2008
Springer
: This paper presents several design issues related to the monolithic integration of a 3-phase AC to DC low voltage, low power rectifier for 3-phase micro source electrical conditi...
APCCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
DAC
1999
ACM
14 years 27 days ago
1999
ACM
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...