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CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
14 years 28 days ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
14 years 24 days ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
AGI
2008
13 years 9 months ago
Temporal Action Logic for Question Answering in an Adventure Game
Inhabiting the complex and dynamic environments of modern computer games with autonomous agents capable of intelligent timely behaviour is a significant research challenge. We illu...
Martin Magnusson, Patrick Doherty
CAV
2005
Springer
133views Hardware» more  CAV 2005»
14 years 1 months ago
On Statistical Model Checking of Stochastic Systems
Statistical methods to model check stochastic systems have been, thus far, developed only for a sublogic of continuous stochastic logic (CSL) that does not have steady state operat...
Koushik Sen, Mahesh Viswanathan, Gul Agha
ASPDAC
2006
ACM
155views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Delay defect screening for a 2.16GHz SPARC64 microprocessor
This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to...
Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hito...