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DATE
2003
IEEE
112views Hardware» more  DATE 2003»
14 years 25 days ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
IPPS
2003
IEEE
14 years 24 days ago
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
R. Achutharaman, R. Govindarajan, G. Hariprakash, ...
CONCUR
1990
Springer
13 years 11 months ago
A Temporal Calculus of Communicating Systems
In this paper we describe the calculus TCCS, an extension of the process algebra CCS with temporal constructs. The calculus is useful for the formal analysis of the timing aspects...
Faron Moller, Chris M. N. Tofts
IPPS
1999
IEEE
13 years 11 months ago
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
Charles Michael Johnston, Anthony T. Chronopoulos
ISPASS
2010
IEEE
13 years 5 months ago
Weak execution ordering - exploiting iterative methods on many-core GPUs
Abstract--On NVIDIA's many-core GPUs, there is no synchronization function among parallel thread blocks. When finegranularity of data communication and synchronization is requ...
Jianmin Chen, Zhuo Huang, Feiqi Su, Jih-Kwon Peir,...