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MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 5 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
ISORC
2007
IEEE
14 years 1 months ago
Experiences from Applying WCET Analysis in Industrial Settings
Knowing the program timing characteristics is fundamental to the successful design and execution of real-time systems. Today, measurement-based timing analysis tools such as in-ci...
Jan Gustafsson, Andreas Ermedahl
IPPS
1999
IEEE
13 years 12 months ago
Scalable Parallelization of Harmonic Balance Simulation
Abstract. A new approach to parallelizing harmonic balance simulation is presented. The technique leverages circuit substructure to expose potential parallelism in the form of a di...
David L. Rhodes, Apostolos Gerasoulis
IEEEPACT
1998
IEEE
13 years 12 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
WCRE
2008
IEEE
14 years 2 months ago
A Business Process Explorer: Recovering Business Processes from Business Applications
A business process contains a set of logically related tasks executed to fulfill business goals. Business applications enable organizations to automatically perform their daily op...
Jin Guo, Ying Zou