1010 search results - page 58 / 202 » Logics for Contravariant Simulations |
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
GECCO
2009
Springer
14 years 2 months ago
2009
Springer
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
AIME
2007
Springer
14 years 2 months ago
2007
Springer
Reification of parthood relations according to the SEP-triplet encoding pattern has been employed in the clinical terminology SNOMED CT to simulate transitivity of the part-of rel...
EUSFLAT
2003
13 years 9 months ago
2003
We report on experiments designed to highlight the strengths and weaknesses of an autonomous rule acquisition algorithm for the fuzzy controller of a simulated mobile robot. The a...
ISCA
1997
IEEE
14 years 8 days ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...