5 search results - page 1 / 1 » Long Round-Trip Time Support with Shared-Memory Crosspoint B... |
HOTI
2005
IEEE
14 years 1 months ago
2005
IEEE
— The amount of memory in buffered crossbars in combined input-crosspoint buffered switches is proportional to the number of crosspoints, or O(N2 ), where N is the number of port...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
— Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N2 × k × L, where N...
HOTI
2002
IEEE
14 years 17 days ago
2002
IEEE
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
LCN
2005
IEEE
14 years 1 months ago
2005
IEEE
A combined input and crosspoint queued (CICQ) switch with a flow control latency of round-trip time (RTT) packets requires each crosspoint (CP) buffer to hold the RTT packets in o...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and lo...