84 search results - page 6 / 17 » Loop Distribution and Fusion with Timing and Code Size Optim... |
ICPPW
2008
IEEE
14 years 1 months ago
2008
IEEE
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
PDP
2006
IEEE
14 years 1 months ago
2006
IEEE
Widespread use of wavelet transforms as in JPEG2000 demands efficient implementations on general purpose computers as well as dedicated hardware. The increasing availability of S...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
Both inherently sequential code and limitations of analysis techniques prevent full parallelization of many applications by parallelizing compilers. Amdahl's Law tells us tha...
TCAD
1998
13 years 7 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...