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» Loop Parallelization Algorithms: From Parallelism Extraction...
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2007
IEEE
14 years 2 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
SC
2003
ACM
14 years 1 months ago
Identifying and Exploiting Spatial Regularity in Data Memory References
The growing processor/memory performance gap causes the performance of many codes to be limited by memory accesses. If known to exist in an application, strided memory accesses fo...
Tushar Mohan, Bronis R. de Supinski, Sally A. McKe...
IEEEPACT
2007
IEEE
14 years 2 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
IEEEPACT
1998
IEEE
14 years 20 days ago
Adaptive Scheduling of Computations and Communications on Distributed Memory Systems
Compile-time scheduling is one approach to extract parallelism which has proved effective when the execution behavior is predictable. Unfortunately, the performance of most priori...
Mayez A. Al-Mouhamed, Homam Najjari
SI3D
2010
ACM
14 years 3 months ago
Stochastic transparency
Stochastic transparency provides a unified approach to orderindependent transparency, anti-aliasing, and deep shadow maps. It augments screen-door transparency using a random sub...
Eric Enderton, Erik Sintorn, Peter Shirley, David ...