83 search results - page 2 / 17 » Loop Pipelining and Optimization for Run Time Reconfiguratio... |
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper, we present a method to estimate the number of reconfiguration steps that a time-constrained algorithm can accommodate. This analysis demonstrates how one would attac...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
Parallelizing compiler technology has improved in recent years. One area in which compilers have made progress is in handling DOACROSS loops, where crossprocessor data dependencie...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
ERSA
2008
13 years 8 months ago
2008
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...